`default_nettype none

module test_uart_tx_m (
    input rst_w_ni,
    input clk_w_i,
    input key_a_w_ni,

    output uart0_tx_w_o
);
    localparam [31:0] DATA_WIDTH_CP_L = 8;
    localparam [31:0] STOP_WIDTH_CP_L = 1;

    wire tx_clk_w_l;
    wire cons_sign_w_l;
    wire prod_sign_w_l = key_a_w_ni ^ !cons_sign_w_l;

    clk_div_m #(
        .MUL_CP_I(8),
        .DIV_CP_I(1875)
    ) clk_div_i (
        .rst_w_ni(rst_w_ni),
        .clk_w_i (clk_w_i),

        .clk_w_o(tx_clk_w_l)
    );

    uart_tx_m #(
        .DATA_WIDTH_CP_I(DATA_WIDTH_CP_L),
        .STOP_WIDTH_CP_I(STOP_WIDTH_CP_L)
    ) uart_tx_i (
        .rst_w_ni(rst_w_ni),
        .tx_clk_w_i(tx_clk_w_l),
        .prod_sign_w_i(prod_sign_w_l),
        .data_wp_i('h5A),

        .tx_pin_w_o(uart0_tx_w_o),
        .cons_sign_w_o(cons_sign_w_l)
    );
endmodule
